FIRRTL

1 program Added 2026-02-11T11:25:19Z Agent: claude-codeModel: sonnetWebSearch: disabled Evidence Report issue View issues
Aliases: Flexible Intermediate Representation for RTL
Provenance: commit a3f72011c0 · authored 2026-02-11T12:25:54+01:00 · agent claude-code · model sonnet

Sources mentioning this language

3 sources · pl_id: pl/firrtl
LLM (this repo) · 1PldbLinguist

Extensions claimed by this language

1 claim. Each row is one upstream assertion with its strength. SWH column shows file occurrences with that extension across the entire archive.
ExtensionSourceStrengthSWH
.firlinguistprimary34.4K files

Related languages

LLVM IR (0.44)PIR (0.42)SPIR-V (0.40)Parrot (0.39)MLIR (0.39)

Real programs from Software Heritage

2 samples mined from derived_datasets/<date>/contents/*.parquet, byte-verified against the SWH archive. Citation-grade qualified SWHIDs preserved.
ZeroWidthIOModule.fir · 554 B · ext .fir · seen 16× in SWH
via unique-primary
swh:1:cnt:611ef9260fcdd91631d3859f0df075640bf02fb6;origin=https://github.com/comparch-security/chipyard-random-llc;anchor=swh:1:rev:fa843cfd41a55be03fa721e2495542925e878b87;path=/tools/treadle/samples/ZeroWidthIOModule.fir
Open in SWH · Raw bytes (SWH) · GitHub raw
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;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2017-09-25 20:31:59.290, builtAtMillis: 1506371519290
circuit ZeroWidthIOModule : 
  module ZeroWidthIOModule : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip zeroIn : UInt<0>, zeroOut : UInt<0>, flip otherIn : UInt<3>, otherOut : UInt<3>}
    
    clock is invalid
    reset is invalid
    io is invalid
    io.zeroOut <= io.zeroIn @[ZeroWidth.scala 15:15]
    io.otherOut <= io.otherIn @[ZeroWidth.scala 16:15]
    
FixedPointDivide.fir · 642 B · ext .fir · seen 16× in SWH
via unique-primary
swh:1:cnt:bd215be4eb34ddf0755025738283e228b174318e;origin=https://github.com/comparch-security/chipyard-random-llc;anchor=swh:1:rev:fa843cfd41a55be03fa721e2495542925e878b87;path=/tools/treadle/samples/FixedPointDivide.fir
Open in SWH · Raw bytes (SWH) · GitHub raw
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;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2017-09-25 20:31:59.290, builtAtMillis: 1506371519290
circuit FixedPointDivide : 
  module FixedPointDivide : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : Fixed<10><<4>>, out : Fixed<10><<4>>}
    
    clock is invalid
    reset is invalid
    io is invalid
    node _T_2 = asUInt(io.in) @[FixedPointSpec.scala 39:20]
    node _T_3 = shr(_T_2, 2) @[FixedPointSpec.scala 39:27]
    node _T_4 = asFixedPoint(_T_3, 4) @[FixedPointSpec.scala 39:55]
    io.out <= _T_4 @[FixedPointSpec.scala 39:10]
    

Programs collected by LLM agents experimental · unverified

Gathered by LLM agents during the experiment that started this catalogue. They are not verified: the agent names an origin, but a program can be altered or invented — an audit found one attributed to a file that does not exist, in a syntax the language does not have. Prefer the programs archived by Software Heritage above. The catalogue's goal is the languages themselves, grounded in sources (PLDB, Wikipedia, Rosetta Code, …), with real archived programs; these examples may be dropped.

Simple Adder

Provenance: commit a3f72011c0 · authored 2026-02-11T12:25:54+01:00 · agent claude-code · model sonnet · WebSearch disabled
code.fir · license: Apache-2.0 · added: 2026-02-11T11:25:19Z
circuit Top :
  module Top :
    input clock : Clock
    input reset : UInt<1>
    input a : UInt<8>
    input b : UInt<8>
    output c : UInt<8>

    node sum = add(a, b)
    c <= sum

Contribute — propose a file extension

Tell us where to find evidence about FIRRTL (mapped to pl/firrtl). A reference URL is required; at least one of extension or program code must be provided too. A maintainer reviews each submission via a draft PR before anything lands.
Optional: attach a program from that URL
If the reference URL points at a single source file you'd like to add as an example program, paste it below. The workflow will write it under languages/FIRRTL/programs/<sha>/. Keep under ~200 lines.
(or open the pre-filled issue directly)
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