TableGen
1 program
Added 2026-03-10T12:00:00Z
Agent: claude-codeModel: claude-sonnet-4-6WebSearch: disabled
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Aliases: LLVM TableGen, tblgen
Provenance: commit 2096cb89e1 · authored 2026-03-10T19:57:20+01:00 · agent claude-code · model claude-sonnet-4-6
Sources mentioning this language
3 sources · pl_id:
pl/llvm-tablegenExtensions claimed by this language
2 claims. Each row is one upstream assertion with its strength.
SWH column shows file occurrences with that extension across the entire archive.| Extension | Source | Strength | SWH |
|---|---|---|---|
.td | linguist | primary | 426.7K files |
.td | pygments | primary | 426.7K files |
Related languages
Real programs from Software Heritage
No SWH evidence indexed yet for this language. (Either the SWH mining hasn't reached this language's extensions, or no matching files exist in the archive.)
Programs collected by LLM agents experimental · unverified
Gathered by LLM agents during the experiment that started this catalogue. They are not verified: the agent names an origin, but a program can be altered or invented — an audit found one attributed to a file that does not exist, in a syntax the language does not have. Prefer the programs archived by Software Heritage above. The catalogue's goal is the languages themselves, grounded in sources (PLDB, Wikipedia, Rosetta Code, …), with real archived programs; these examples may be dropped.
Register Class Definition
Provenance: commit 2096cb89e1 · authored 2026-03-10T19:57:20+01:00 · agent claude-code · model claude-sonnet-4-6 · WebSearch disabled
// Simple register definitions in TableGen (LLVM's domain-specific language)
class Register<string name, list<string> altNames = []> {
string AsmName = name;
list<string> AltNames = altNames;
}
class RegisterClass<list<Register> regs, int alignment> {
list<Register> MemberList = regs;
int Alignment = alignment;
}
// Define individual 64-bit general-purpose registers
def X0 : Register<"x0">;
def X1 : Register<"x1">;
def X2 : Register<"x2">;
def X3 : Register<"x3">;
def X4 : Register<"x4">;
def SP : Register<"sp", ["x31"]>;
// Define a register class for 64-bit general-purpose registers
def GPR64 : RegisterClass<[X0, X1, X2, X3, X4], 64>;