Veryl

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LLM-contributed programs

module Counter (
    i_clk: input logic,
    i_rst: input logic,
    o_count: output logic<8>
) {
    var count: logic<8>;

    always_ff (i_clk, i_rst) {
        if_reset {
            count = 0;
        } else {
            count += 1;
        }
    }

    assign o_count = count;
}

Real programs from Software Heritage

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