R

% Generated by roxygen2: do not edit by hand
% Please edit documentation in R/cyto_gate-helpers.R
\name{cyto_gate_type}
\alias{cyto_gate_type}
\title{Get Gate Type from Saved Gate.}
\usage{
cyto_gate_type(gates)
}
\arguments{
\item{gates}{an object of class \code{filters} containing the gates from
which the \code{type(s)} must be obtained.}
}
\value{
vector of gate type names for supplied gates.
}
\description{
Get Gate Type from Saved Gate.
}
\examples{
library(CytoExploreRData)

# Load in samples
fs <- Activation
gs <- GatingSet(fs)

# Apply compensation
gs <- cyto_compensate(gs)

# Transform fluorescent channels
gs <- cyto_transform(gs)

# Gate using cyto_gate_draw
gt <- Activation_gatingTemplate
gt_gating(gt, gs)

# Get gate type used for T Cells gate
cyto_gate_type(gs_pop_get_gate(gs, "Cells")[[1]])
cyto_gate_type(gs_pop_get_gate(gs, "T Cells")[[1]])
cyto_gate_type(gs_pop_get_gate(gs, "CD69+ CD4 T Cells")[[1]])
}
\author{
Dillon Hammill, \email{Dillon.Hammill@anu.edu.au}
}

/*
 * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_v3.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"

/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif

/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif

cpu_reset_prologue neoverse_v3

.global check_erratum_neoverse_v3_3701767

workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647
	/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
	ldr x0, =0x1
	msr S3_6_c15_c8_0, x0 	/* msr CPUPSELR_EL3, X0 */
	ldr x0, =0xd5380000
	msr S3_6_c15_c8_2, x0 	/* msr CPUPOR_EL3, X0 */
	ldr x0, =0xFFFFFF40
	msr S3_6_c15_c8_3,x0 	/* msr CPUPMR_EL3, X0 */
	ldr x0, =0x000080010033f
	msr S3_6_c15_c8_1, x0	/* msr CPUPCR_EL3, X0 */
	isb
workaround_reset_end neoverse_v3, ERRATUM(2970647)

check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0)

add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767

check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)

/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
	sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46)
workaround_reset_end neoverse_v3, CVE(2024, 5660)

check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1)

	/* ----------------------------------------------------------------
	 * CVE-2024-7881 is mitigated for Neoverse-V3 / Neoverse-V3AE
	 * using erratum 3696307 workaround by disabling the
	 * affected prefetcher setting CPUACTLR6_EL1[41].
	 * ----------------------------------------------------------------
	 */
workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
       sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41)
workaround_reset_end neoverse_v3, CVE(2024, 7881)

check_erratum_ls neoverse_v3, CVE(2024, 7881), CPU_REV(0, 1)

	/* ---------------------------------------------
	 * HW will do the cache maintenance while powering down
	 * ---------------------------------------------
	 */
func neoverse_v3_core_pwr_dwn
	/* ---------------------------------------------
	 * Enable CPU power down bit in power control register
	 * ---------------------------------------------
	 */
	sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
		NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT

	isb
	ret
endfunc neoverse_v3_core_pwr_dwn

cpu_reset_func_start neoverse_v3
	/* Disable speculative loads */
	msr	SSBS, xzr
cpu_reset_func_end neoverse_v3

	/* ---------------------------------------------
	 * This function provides Neoverse V3 specific
	 * register information for crash reporting.
	 * It needs to return with x6 pointing to
	 * a list of register names in ascii and
	 * x8 - x15 having values of registers to be
	 * reported.
	 * ---------------------------------------------
	 */
.section .rodata.neoverse_v3_regs, "aS"
neoverse_v3_regs:  /* The ascii list of register names to be reported */
	.asciz	"cpuectlr_el1", ""

func neoverse_v3_cpu_reg_dump
	adr	x6, neoverse_v3_regs
	mrs	x8, NEOVERSE_V3_CPUECTLR_EL1
	ret
endfunc neoverse_v3_cpu_reg_dump

declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
	neoverse_v3_reset_func, \
	neoverse_v3_core_pwr_dwn

declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
	neoverse_v3_reset_func, \
	neoverse_v3_core_pwr_dwn

% Generated by roxygen2: do not edit by hand
% Please edit documentation in R/Misc_Internal.R
\name{getmov2}
\alias{getmov2}
\title{Optimization function to find a movement model that matches user specified
movement characteristics modified for Rcpp.}
\usage{
getmov2(x, Prob_staying, Frac_area_1)
}
\arguments{
\item{x}{A position in vectors Prob_staying and Frac_area_1}

\item{Prob_staying}{User specified probability that individuals in area 1
remain in that area (unfished conditions)}

\item{Frac_area_1}{User specified fraction of individuals found in area 1
(unfished conditions)}
}
\value{
A markov movement matrix
}
\description{
The user specifies the probability of staying in the same area and spatial
heterogeneity (both in the unfished state).
}
\details{
This is paired with movfit to find the correct movement model.
}
\examples{

Prob_staying<-0.8 # probability  that individuals remain in area 1 between time-steps
Frac_area_1<-0.35 # the fraction of the stock found in area 1 under equilibrium conditions
markovmat<-getmov2(1,Prob_staying, Frac_area_1)
vec<-c(0.5,0.5) # initial guess at equilibrium distribution (2 areas)
for(i in 1:300)vec<-apply(vec*markovmat,2,sum) # numerical approximation to stable distribution
c(markovmat[1,1],vec[1]) # pretty close right?


}
\author{
T. Carruthers
}