swh:1:cnt:b2005fc5c6d42a9fc23bcea738c710e70eaa095c;origin=https://github.com/suisuisi/FPGA_Library;anchor=swh:1:rev:d95b04432091b7498f2233ee55743a022f64c7ad;path=/ThreePart/digilent_ip/ip/Pmods/PmodOLED_v1_0/src/PmodOLED_ooc.xdc
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################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name ext_spi_clk -period 10 [get_ports ext_spi_clk]
create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]
################################################################################
swh:1:cnt:9ae7bee9a3b48816f3c978ed6af17aa9de1c4efc;origin=https://github.com/MinimalOS/arm-linux-androideabi-4.9;anchor=swh:1:rev:70f01eba6b3bcfc8825ceffa01244f5f85908559;path=/arm-linux-androideabi/lib/ldscripts/elf32tilegx_be.xdc
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/* Script for -pie -z combreloc: position independent executable, combine & sort relocs */
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