AHDL
1 program
Added 2025-11-07T10:41:17Z
Model: google/gemini-2.5-proTemp: 0.4
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Aliases: Altera Hardware Description Language
Provenance: commit 17daa88e9c · authored 2025-11-07T11:41:17+01:00 · model google/gemini-2.5-pro
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3 sources · pl_id:
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4-bit Synchronous Counter in AHDL
Provenance: commit 17daa88e9c · authored 2025-11-07T11:41:17+01:00 · model google/gemini-2.5-pro · Temp 0.4
-- AHDL TDF for a 4-bit counter with synchronous reset
--
-- ECE 379, University of British Columbia
--
-- This counter has a single clock input, a synchronous reset,
-- and a 4-bit output.
SUBDESIGN counter
(
clk : INPUT;
reset : INPUT;
q[3..0] : OUTPUT;
)
VARIABLE
q[3..0] : DFF;
BEGIN
q[].clk = clk;
IF reset THEN
q[].d = 0;
ELSE
q[].d = q[].q + 1;
END IF;
END;