VHDL
1 program
Added 2025-10-22T13:06:49Z
Model: anthropic/claude-3.5-sonnetTemp: 0.4
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Aliases: VHSIC Hardware Description Language
Provenance: commit a818fca9b9 · authored 2025-10-22T15:06:49+02:00 · model anthropic/claude-3.5-sonnet
Sources mentioning this language
6 sources · pl_id:
pl/vhdlExtensions claimed by this language
10 claims. Each row is one upstream assertion with its strength.
SWH column shows file occurrences with that extension across the entire archive.| Extension | Source | Strength | SWH |
|---|---|---|---|
.vhdl | linguist | primary | 710.2K files |
.vhdl | pygments | primary | 710.2K files |
.vhd | linguist | secondary | 2.9M files |
.vhd | pygments | secondary | 2.9M files |
.vhf | linguist | secondary | 6.3K files |
.vhi | linguist | secondary | 4.0K files |
.vho | linguist | secondary | 239.5K files |
.vhs | linguist | secondary | 201 files |
.vht | linguist | secondary | 10.6K files |
.vhw | linguist | secondary | 2.7K files |
Related languages
Real programs from Software Heritage
No SWH evidence indexed yet for this language. (Either the SWH mining hasn't reached this language's extensions, or no matching files exist in the archive.)
Programs collected by LLM agents experimental · unverified
Gathered by LLM agents during the experiment that started this catalogue. They are not verified: the agent names an origin, but a program can be altered or invented — an audit found one attributed to a file that does not exist, in a syntax the language does not have. Prefer the programs archived by Software Heritage above. The catalogue's goal is the languages themselves, grounded in sources (PLDB, Wikipedia, Rosetta Code, …), with real archived programs; these examples may be dropped.
Simple 4-bit Counter
Provenance: commit a818fca9b9 · authored 2025-10-22T15:06:49+02:00 · model anthropic/claude-3.5-sonnet · Temp 0.4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal counter_up : std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if(reset='1') then
counter_up <= "0000";
elsif(rising_edge(clk)) then
counter_up <= counter_up + 1;
end if;
end process;
counter_out <= counter_up;
end Behavioral;