HHDL
1 program
Added 2026-03-05T12:00:00Z
Agent: claude-codeModel: claude-sonnet-4-6WebSearch: enabled
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Aliases: Haskell Hardware Design Language, Haskell Hardware Description Language
Provenance: commit 941974f462 · authored 2026-03-05T12:45:05+01:00 · agent claude-code · model claude-sonnet-4-6
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Running Sum (Accumulator)
Provenance: commit 941974f462 · authored 2026-03-05T12:45:05+01:00 · agent claude-code · model claude-sonnet-4-6 · WebSearch enabled
{-# LANGUAGE TypeFamilies, TypeOperators, FlexibleContexts, DoRec #-}
{-# LANGUAGE DeriveDataTypeable, NoImplicitPrelude, TemplateHaskell #-}
{-# LANGUAGE UndecidableInstances #-}
module Hardware.HHDL.Examples.RunningSum where
import Data.Word
import Hardware.HHDL
import Hardware.HHDL.Examples.Clock
import Hardware.HHDL.Examples.SimpleSum
-------------------------------------------------------------------------------
-- Running polymorphic sum, ie, accumulator.
-- Demonstrates registers.
runningSumRec :: (Show a, ClockAllowed c clks, BitRepr a, Arith a) => Clocked clks (Wire c a :. Nil) (Wire c a :. Nil)
runningSumRec = mkClocked "runningSum" $ \(a :. Nil) -> do
rec
sum <- register (fromIntegerLit 0) nextSum
(nextSum :. Nil) <- instantiate simpleSum (a :. sum :. Nil)
return $ sum :. Nil
runningSumRecVHDLText = writeHDLText VHDL (runningSumRec :: Clocked (Clk :. Nil) (Wire Clk Word8 :. Nil) (Wire Clk Word8 :. Nil))
(\s -> putStrLn s >> writeFile "runningSum.vhdl" s)
test = runningSumRecVHDLText