SystemVerilog

1 program Added 2025-10-23T10:35:51Z Model: x-ai/grok-4-fastTemp: 0.4 Evidence Report issue View issues
Aliases: —
Provenance: commit 92069f2b53 · authored 2025-10-23T12:35:51+02:00 · model x-ai/grok-4-fast

Sources mentioning this language

8 sources · pl_id: pl/systemverilog
LLM (this repo) · 1PldbLinguistPygmentsWikipediaHyperpolyglotRosettacodeWikidata · Q1387402

Wikipedia infobox

Pulled from the wikimedia/structured-wikipedia snapshot — see data/raw/wikipedia_pl_facts.*.jsonl and pl_fact.csv for the long-table provenance.

Paradigmsstructured (design) object-oriented (verification)
Typingstatic, weak
Designed bySynopsys · later IEEE
First appeared2002
Influenced byVerilog · VHDL · C++ (design) OpenVera · Java (verification)

Extensions claimed by this language

8 claims. Each row is one upstream assertion with its strength. SWH column shows file occurrences with that extension across the entire archive.
ExtensionSourceStrengthSWH
.svlinguistprimary1.2M files
.svpygmentsprimary1.2M files
.svwikidataprimary1.2M files
.svrwikidataprimary4.9K files
.svhlinguistsecondary48.7K files
.svhpygmentssecondary48.7K files
.vhlinguistsecondary37.3K files
.svhwikipediaproposed48.7K files

Related languages

Bluespec SystemVerilog (0.43)BSV (0.42)SystemC (0.33)Bluespec (0.30)SystemTap (0.26)

LLM-contributed programs

Simple Register with Synchronous Reset

Provenance: commit 92069f2b53 · authored 2025-10-23T12:35:51+02:00 · model x-ai/grok-4-fast · Temp 0.4
code.sv · added: 2025-10-23T10:35:51Z
// This is an example of a simple register with synchronous reset
module simple_register (
    input  logic        clk,
    input  logic        rst_n,
    input  logic [7:0]  data_in,
    output logic [7:0]  data_out
);

    always_ff @(posedge clk) begin
        if (!rst_n)
            data_out <= 8'b0;
        else
            data_out <= data_in;
    end

endmodule

Real programs from Software Heritage

2 samples mined from derived_datasets/<date>/contents/*.parquet, byte-verified against the SWH archive. Citation-grade qualified SWHIDs preserved.
scr1_search_ms1.svh · 2806 B · ext .svh · seen 59× in SWH
via fallback
swh:1:cnt:8ba97c2758e54c531c6ca43c6d31f3397756f11a;origin=https://github.com/syntacore/scr1;anchor=swh:1:rev:a20ea056631306c2d24ff0f36961b36ffc799fc6;path=/src/includes/scr1_search_ms1.svh
Open in SWH · Raw bytes (SWH) · GitHub raw
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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file       <scr1_search_ms1.svh>
/// @brief      Most significant one search function
///

`ifndef SCR1_SEARCH_MS1_SVH
`define SCR1_SEARCH_MS1_SVH

//-------------------------------------------------------------------------------
// Local types declaration
//-------------------------------------------------------------------------------
typedef struct {
    logic       vd;
    logic       idx;
} type_scr1_search_one_2_s;

typedef struct {
    logic           vd;
    logic [4:0]     idx;
} type_scr1_search_one_32_s;

//-------------------------------------------------------------------------------
// Leading Zeros Count Function
//-------------------------------------------------------------------------------
function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2(
    input   logic [1:0]     din
);
    type_scr1_search_one_2_s tmp;
begin
    tmp.vd  = |din;
    tmp.idx = ~din[1];
    return  tmp;
end
endfunction : scr1_lead_zeros_cnt_2

function automatic logic [4:0] scr1_lead_zeros_cnt_32(
    input   logic [31:0]    din
);
begin
    logic [15:0]    stage1_vd;
    logic [7:0]     stage2_vd;
    logic [3:0]     stage3_vd;
    logic [1:0]     stage4_vd;

    logic           stage1_idx [15:0];
    logic [1:0]     stage2_idx [7:0];
    logic [2:0]     stage3_idx [3:0];
    logic [3:0]     stage4_idx [1:0];
    type_scr1_search_one_32_s tmp;
    logic [4:0]     res;

    // Stage 1
    for (int unsigned i=0; i<16; ++i) begin
        type_scr1_search_one_2_s tmp;
        tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]);
        stage1_vd[i]  = tmp.vd;
        stage1_idx[i] = tmp.idx;
    end

    // Stage 2
    for (int unsigned i=0; i<8; ++i) begin
        type_scr1_search_one_2_s tmp;
        tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]);
        stage2_vd[i]  = tmp.vd;
        stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
    end

    // Stage 3
    for (int unsigned i=0; i<4; ++i) begin
        type_scr1_search_one_2_s tmp;
        tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]);
        stage3_vd[i]  = tmp.vd;
        stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
    end

    // Stage 4
    for (int unsigned i=0; i<2; ++i) begin
        type_scr1_search_one_2_s tmp;
        tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]);
        stage4_vd[i]  = tmp.vd;
        stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]};
    end

    // Stage 5
    tmp.vd = |stage4_vd;
    tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]};

    res = tmp.idx;

    return res;
end
endfunction : scr1_lead_zeros_cnt_32

`endif // SCR1_SEARCH_MS1_SVH
fftw.sv · 2541 B · ext .sv · seen 50× in SWH
via unique-primary
swh:1:cnt:c1bda654250570a30b897eb263aa0353093f4bfb;origin=https://github.com/phucducnguyen/uvm-fft-ofdm;anchor=swh:1:rev:86775bdc37e79a41a640a7bc3a36005d8c8a916e;path=/fftw.sv
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// output is real, imag
// real is rv[45:23]
// imag is rv[22:0]
function reg [45:0] fftwiddle(reg [5:0] ix);
  reg [45:0] rv;
  case(ix)
    0 : rv={23'd32768, 23'd0};
    1 : rv={23'd32728, -23'd1607};
    2 : rv={23'd32610, -23'd3211};
    3 : rv={23'd32413, -23'd4808};
    4 : rv={23'd32138, -23'd6392};
    5 : rv={23'd31785, -23'd7961};
    6 : rv={23'd31357, -23'd9512};
    7 : rv={23'd30852, -23'd11039};
    8 : rv={23'd30273, -23'd12539};
    9 : rv={23'd29621, -23'd14010};
    10 : rv={23'd28898, -23'd15446};
    11 : rv={23'd28106, -23'd16846};
    12 : rv={23'd27245, -23'd18204};
    13 : rv={23'd26319, -23'd19519};
    14 : rv={23'd25330, -23'd20787};
    15 : rv={23'd24279, -23'd22005};
    16 : rv={23'd23170, -23'd23170};
    17 : rv={23'd22005, -23'd24279};
    18 : rv={23'd20787, -23'd25330};
    19 : rv={23'd19519, -23'd26319};
    20 : rv={23'd18204, -23'd27245};
    21 : rv={23'd16846, -23'd28106};
    22 : rv={23'd15446, -23'd28898};
    23 : rv={23'd14010, -23'd29621};
    24 : rv={23'd12539, -23'd30273};
    25 : rv={23'd11039, -23'd30852};
    26 : rv={23'd9512, -23'd31357};
    27 : rv={23'd7961, -23'd31785};
    28 : rv={23'd6392, -23'd32138};
    29 : rv={23'd4808, -23'd32413};
    30 : rv={23'd3211, -23'd32610};
    31 : rv={23'd1607, -23'd32728};
    32 : rv={23'd0, -23'd32768};
    33 : rv={-23'd1607, -23'd32728};
    34 : rv={-23'd3211, -23'd32610};
    35 : rv={-23'd4808, -23'd32413};
    36 : rv={-23'd6392, -23'd32138};
    37 : rv={-23'd7961, -23'd31785};
    38 : rv={-23'd9512, -23'd31357};
    39 : rv={-23'd11039, -23'd30852};
    40 : rv={-23'd12539, -23'd30273};
    41 : rv={-23'd14010, -23'd29621};
    42 : rv={-23'd15446, -23'd28898};
    43 : rv={-23'd16846, -23'd28106};
    44 : rv={-23'd18204, -23'd27245};
    45 : rv={-23'd19519, -23'd26319};
    46 : rv={-23'd20787, -23'd25330};
    47 : rv={-23'd22005, -23'd24279};
    48 : rv={-23'd23170, -23'd23170};
    49 : rv={-23'd24279, -23'd22005};
    50 : rv={-23'd25330, -23'd20787};
    51 : rv={-23'd26319, -23'd19519};
    52 : rv={-23'd27245, -23'd18204};
    53 : rv={-23'd28106, -23'd16846};
    54 : rv={-23'd28898, -23'd15446};
    55 : rv={-23'd29621, -23'd14010};
    56 : rv={-23'd30273, -23'd12539};
    57 : rv={-23'd30852, -23'd11039};
    58 : rv={-23'd31357, -23'd9512};
    59 : rv={-23'd31785, -23'd7961};
    60 : rv={-23'd32138, -23'd6392};
    61 : rv={-23'd32413, -23'd4808};
    62 : rv={-23'd32610, -23'd3211};
    63 : rv={-23'd32728, -23'd1607};
  endcase
  return rv;
endfunction : fftwiddle

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