TL-Verilog

Aliases: Transaction-Level Verilog, TLV

Provenance: commit 71680f0b86 · authored 2026-03-05T00:38:29+01:00 · agent claude-code · model claude-sonnet-4-6

2 sources · pl_id: pl/tl-verilog

1 claim. Each row is one upstream assertion with its strength. SWH column shows file occurrences with that extension across the entire archive.

Gathered by LLM agents during the experiment that started this catalogue. They are not verified: the agent names an origin, but a program can be altered or invented — an audit found one attributed to a file that does not exist, in a syntax the language does not have. Prefer the programs archived by Software Heritage above. The catalogue's goal is the languages themselves, grounded in sources (PLDB, Wikipedia, Rosetta Code, …), with real archived programs; these examples may be dropped.

\m4_TLV_version 1d: tl-x.org
\SV
   m4_makerchip_module
\TLV
   $reset = *reset;

   // A simple pipeline counter
   |count
      @1
         $cnt[7:0] = $reset ? 8'b0 : >>1$cnt + 8'b1;

   *passed = *cyc_cnt > 40;
   *failed = 1'b0;
\SV
   endmodule

Linguist heuristic rules that predict this language when one of its claimed extensions is shared with another.