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TL-Verilog

1 program Added 2026-03-05T10:00:00Z Agent: claude-codeModel: claude-sonnet-4-6WebSearch: disabled Evidence Report issue View issues

Aliases: Transaction-Level Verilog, TLV

Provenance: commit 71680f0b86 · authored 2026-03-05T00:38:29+01:00 · agent claude-code · model claude-sonnet-4-6

Sources mentioning this language

2 sources · pl_id: pl/tl-verilog

LLM (this repo) · 1 Linguist

Extensions claimed by this language

1 claim. Each row is one upstream assertion with its strength. SWH column shows file occurrences with that extension across the entire archive.

Extension	Source	Strength	SWH
`.tlv`	linguist	primary	14.5K files

Related languages

Transact-SQL (0.19)TAL (0.19)Verilog-A (0.16)TACPOL (0.15)Verilog-AMS (0.15)

LLM-contributed programs

Pipeline Counter

Origin · Download · manifest.json · Report

Provenance: commit 71680f0b86 · authored 2026-03-05T00:38:29+01:00 · agent claude-code · model claude-sonnet-4-6 · WebSearch disabled

code.tlv · added: 2026-03-05T10:00:00Z

\m4_TLV_version 1d: tl-x.org
\SV
   m4_makerchip_module
\TLV
   $reset = *reset;

   // A simple pipeline counter
   |count
      @1
         $cnt[7:0] = $reset ? 8'b0 : >>1$cnt + 8'b1;

   *passed = *cyc_cnt > 40;
   *failed = 1'b0;
\SV
   endmodule

Real programs from Software Heritage

No SWH evidence indexed yet for this language. (Either the SWH mining hasn't reached this language's extensions, or no matching files exist in the archive.)

Disambiguation rules

Linguist heuristic rules that predict this language when one of its claimed extensions is shared with another.

Rule	Ext	Kind	Predicates (truncated)
`h/linguist/.tlv/0`	`.tlv`	predicates	`[{"kind": "any", "regexes": ["^\\\\.{0,10}TLV_version"]}]`

Contribute — propose a file extension

Tell us where to find evidence about TL-Verilog (mapped to pl/tl-verilog). A reference URL is required; at least one of extension or program code must be provided too. A maintainer reviews each submission via a draft PR before anything lands.

File extension (optional) — e.g. .oak. Some PLs (e.g. esolangs) have no convention; leave empty if so. Friendly name (optional)

Reference URL * — public URL where the extension is used (GitHub file, GitLab, spec page, …) Notes (optional) — 1–3 sentences if context helps the maintainer

Optional: attach a program from that URL

If the reference URL points at a single source file you'd like to add as an example program, paste it below. The workflow will write it under languages/TL-Verilog/programs/<sha>/. Keep under ~200 lines.

Title (optional) — e.g. "Factorial", "Quicksort" License guess (optional) — MIT, GPL-2.0, …

Code (optional) — paste verbatim bytes from the reference URL

(or open the pre-filled issue directly)