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Verilog-AMS

1 program Added 2026-02-12T10:37:57Z Agent: claude-codeModel: sonnetWebSearch: disabled Evidence Report issue View issues

Aliases: Verilog AMS, Verilog-A/MS

Provenance: commit 39a6c277e6 · authored 2026-02-12T11:38:57+01:00 · agent claude-code · model sonnet

Sources mentioning this language

1 source · not in taxonomy (canonical name didn't match any upstream)

LLM (this repo) · 1

Related languages

Verilog-A (0.42)VHDL-AMS (0.26)Verilog (0.22)SystemVerilog (0.21)Verus (0.17)

LLM-contributed programs

Simple Resistor Model

Origin · Download · manifest.json · Report

Provenance: commit 39a6c277e6 · authored 2026-02-12T11:38:57+01:00 · agent claude-code · model sonnet · WebSearch disabled

code.vams · added: 2026-02-12T10:37:57Z

`include "disciplines.vams"

module resistor(p, n);
    parameter real R = 1.0k from (0:inf);
    inout p, n;
    electrical p, n;
    analog begin
        I(p, n) <+ V(p, n) / R;
    end
endmodule

Contribute — propose a file extension

Tell us where to find evidence about Verilog-AMS (mapped to pl/verilog_ams). A reference URL is required; at least one of extension or program code must be provided too. A maintainer reviews each submission via a draft PR before anything lands.

File extension (optional) — e.g. .oak. Some PLs (e.g. esolangs) have no convention; leave empty if so. Friendly name (optional)

Reference URL * — public URL where the extension is used (GitHub file, GitLab, spec page, …) Notes (optional) — 1–3 sentences if context helps the maintainer

Optional: attach a program from that URL

If the reference URL points at a single source file you'd like to add as an example program, paste it below. The workflow will write it under languages/Verilog-AMS/programs/<sha>/. Keep under ~200 lines.

Title (optional) — e.g. "Factorial", "Quicksort" License guess (optional) — MIT, GPL-2.0, …

Code (optional) — paste verbatim bytes from the reference URL

(or open the pre-filled issue directly)