Verilog-A

Aliases: Verilog A, VerilogA

Provenance: commit 251a39792c · authored 2026-02-05T21:49:52+01:00 · agent systems_niche · model codex_default

1 source · not in taxonomy (canonical name didn't match any upstream)

Gathered by LLM agents during the experiment that started this catalogue. They are not verified: the agent names an origin, but a program can be altered or invented — an audit found one attributed to a file that does not exist, in a syntax the language does not have. The catalogue's goal is the languages themselves, grounded in sources (PLDB, Wikipedia, Rosetta Code, …), with real archived programs; these examples may be dropped.

`include "constants.vams"
`include "disciplines.vams"

module resistor(p, n);
  inout p, n;
  electrical p, n;
  parameter real R = 1k;

  analog begin
    I(p, n) <+ V(p, n) / R;
  end
endmodule